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<a href="#pub-attribs">成员变量</a>  </div>
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<div class="title">SCB_Type结构体 参考<div class="ingroups"><a class="el" href="group___c_m_s_i_s__core__register.html">Defines and Type Definitions</a> &raquo; <a class="el" href="group___c_m_s_i_s___s_c_b.html">System Control Block (SCB)</a></div></div>  </div>
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<p>Structure type to access the System Control Block (SCB).  
 <a href="struct_s_c_b___type.html#details">更多...</a></p>

<p><code>#include &lt;<a class="el" href="core__cm0plus_8h_source.html">core_cm0plus.h</a>&gt;</code></p>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
成员变量</h2></td></tr>
<tr class="memitem:adbf8292503748ba6421a523bdee6819d"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#adbf8292503748ba6421a523bdee6819d">CPUID</a></td></tr>
<tr class="separator:adbf8292503748ba6421a523bdee6819d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aced895d6aba03d72b0d865fcc5ce44ee"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#aced895d6aba03d72b0d865fcc5ce44ee">ICSR</a></td></tr>
<tr class="separator:aced895d6aba03d72b0d865fcc5ce44ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af86c61a5d38a4fc9cef942a12744486b"><td class="memItemLeft" align="right" valign="top"><a id="af86c61a5d38a4fc9cef942a12744486b"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><b>RESERVED0</b></td></tr>
<tr class="separator:af86c61a5d38a4fc9cef942a12744486b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9b6ccd9c0c0865f8facad77ea37240b0"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a9b6ccd9c0c0865f8facad77ea37240b0">AIRCR</a></td></tr>
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<tr class="memitem:acac65f229cb3fcb5369a0a9e0393b8c0"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#acac65f229cb3fcb5369a0a9e0393b8c0">SCR</a></td></tr>
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<tr class="memitem:ad68b5c1f2d9845ef4247cf2d9b041336"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#ad68b5c1f2d9845ef4247cf2d9b041336">CCR</a></td></tr>
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<tr class="memitem:ac4ac04e673b5b8320d53f7b0947db902"><td class="memItemLeft" align="right" valign="top"><a id="ac4ac04e673b5b8320d53f7b0947db902"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><b>RESERVED1</b></td></tr>
<tr class="separator:ac4ac04e673b5b8320d53f7b0947db902"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9976ebb49caa4da93e1dad137071b9ee"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a9976ebb49caa4da93e1dad137071b9ee">SHP</a> [2U]</td></tr>
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<tr class="memitem:a44ad5c292dbd77e72f310902375a8a06"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a44ad5c292dbd77e72f310902375a8a06">SHCSR</a></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">详细描述</h2>
<div class="textblock"><p>Structure type to access the System Control Block (SCB). </p>
</div><h2 class="groupheader">结构体成员变量说明</h2>
<a id="a9b6ccd9c0c0865f8facad77ea37240b0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9b6ccd9c0c0865f8facad77ea37240b0">&#9670;&nbsp;</a></span>AIRCR</h2>

<div class="memitem">
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          <td class="memname">__IOM uint32_t AIRCR</td>
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<p>Offset: 0x00C (R/W) Application Interrupt and Reset Control Register </p>

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<a id="ad68b5c1f2d9845ef4247cf2d9b041336"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ad68b5c1f2d9845ef4247cf2d9b041336">&#9670;&nbsp;</a></span>CCR</h2>

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          <td class="memname">__IOM uint32_t CCR</td>
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<p>Offset: 0x014 (R/W) Configuration Control Register </p>

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<a id="adbf8292503748ba6421a523bdee6819d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#adbf8292503748ba6421a523bdee6819d">&#9670;&nbsp;</a></span>CPUID</h2>

<div class="memitem">
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          <td class="memname">__IM uint32_t CPUID</td>
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<p>Offset: 0x000 (R/ ) CPUID Base Register </p>

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<a id="aced895d6aba03d72b0d865fcc5ce44ee"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aced895d6aba03d72b0d865fcc5ce44ee">&#9670;&nbsp;</a></span>ICSR</h2>

<div class="memitem">
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          <td class="memname">__IOM uint32_t ICSR</td>
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<p>Offset: 0x004 (R/W) Interrupt Control and State Register </p>

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<a id="acac65f229cb3fcb5369a0a9e0393b8c0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#acac65f229cb3fcb5369a0a9e0393b8c0">&#9670;&nbsp;</a></span>SCR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">__IOM uint32_t SCR</td>
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<p>Offset: 0x010 (R/W) System Control Register </p>

</div>
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<a id="a44ad5c292dbd77e72f310902375a8a06"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a44ad5c292dbd77e72f310902375a8a06">&#9670;&nbsp;</a></span>SHCSR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">__IOM uint32_t SHCSR</td>
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      </table>
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<p>Offset: 0x024 (R/W) System Handler Control and State Register </p>

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<a id="a9976ebb49caa4da93e1dad137071b9ee"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9976ebb49caa4da93e1dad137071b9ee">&#9670;&nbsp;</a></span>SHP</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">__IOM uint32_t SHP[2U]</td>
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<p>Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED </p>

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